The technique disclosed in the present invention relates to semiconductor devices and design methods thereof.
In recent years, miniaturization has rapidly progressed in the field of semiconductor devices. However, reducing the cell height of standard cells, etc. reduces flexibility of interconnect design. Thus, a technique has been proposed which increases the flexibility of interconnect design by connecting a power supply region to active regions of transistors by using silicide interconnects (see, e.g., Japanese Patent Publication No. 2001-68653).
FIG. 3 shows a conventional semiconductor device 120 having a structure that connects power supply regions to active regions of transistors by using silicide interconnects.
As shown in FIG. 3, a P-type impurity diffusion region 113 is divided into three regions, namely a source region S and two drain regions D, by gate electrodes 111, 112, and forms a P-type transistor group 121. The P-type impurity diffusion region 113 is electrically connected to a power supply interconnect 123 provided in a power supply interconnect region 117, via a contact portion 125 provided in a silicidated extended portion 113a in the P-type impurity diffusion region 113. Similarly, an N-type impurity diffusion region 116 is divided into three regions, namely a source region S and two drain regions D, by gate electrodes 114, 115, and forms an N-type transistor group 122. The N-type impurity diffusion region 116 is electrically connected to a power supply interconnect 124 provided in a power supply interconnect region 118, via a contact portion 126 provided in a silicidated extended portion 116a in the N-type impurity diffusion region 116. Note that reference characters 127, 128 represent interconnects. Thus, the conventional semiconductor device uses the silicidated extended portions 113a, 116a as silicide interconnects to increase interconnect efficiency and flexibility of interconnect design.